ds28c22 deepcover secure memory with i 2 c sha-256 and 3kb user eeprom general description deepcover m embedded security solutions cloak sensi - tive data under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure memory (ds28c22) combines crypto-strong, bidirectional, secure challenge-and- response authentication and small message encryption functionality with an implementation based on the fips 180-specified secure hash algorithm (sha-256). a 3kb user-programmable eeprom array provides nonvola - tile storage for application data and additional protected memory holds a read-protected secret for sha-256 oper - ations and settings for user memory control. each device has its own guaranteed unique and unalterable 64-bit rom identification number (rom id) that is factory pro - grammed into the chip. this unique rom id is used as a fundamental input parameter for cryptographic operations and also serves as an electronic serial number within the application. a bidirectional security model enables two- way authentication and encryption between a host system and slave-embedded ds28c22. slave-to-host authenti - cation is used by a host system to securely validate that an attached or embedded ds28c22 is authentic. host- to-slave authentication is used to protect ds28c22 user memory from being modified by a nonauthentic host. the sha-256 message authentication code (mac), which the ds28c22 generates, is computed from data in the user memory, an on-chip secret, a host random challenge, and the 64-bit rom id. the device also facilitates encrypted read and write between host and slave using a one time pad computed by the sha-256 engine. when not in use, the ds28c22 can be put in sleep mode where power consumption is minimal. applications authentication of network-attached appliances system intellectual property protection secure feature setting for conigurable systems key generation and secure exchange for crypto - graphic systems beneits and features symmetric key-based bidirectional secure authentication and encryption model based on sha-256 dedicated hardware-accelerated sha engine for generating sha-256 macs strong authentication with a 256-bit, user- programmable secret, and input challenge 3072 bits of user eeprom partitioned into 12 pages of 256 bits user-programmable and irreversible eeprom protection modes including authentication, write and read protect, encryption, and otp/eprom emulation supports 100khz and 400khz i 2 c communication speeds supports power-saving sleep mode at 0.5a (typ) operating range: 3.3v 10%, -40c to +85c 8-pin tdfn package 219-0029; rev 2; 7/13 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/ds28c22.related . typical application circuit deepcover is a registered trademark of maxim integrated products, inc. evaluation kit available sda v cc scl slpz r p r p = 1.1k maximum i 2 c bus capacitance 320pf 3.3v c (i 2 c port) ds28c22 abridged data sheet downloaded from: http:///
ds28c22 deepcover secure memory with i 2 c sha-256 and 3kb user eeprom www.maximintegrated.com maxim integrated 2 electrical characteristics (t a = -40c to +85c, unless otherwise noted.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51- 7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . voltage range on any pin relative to gnd ........ -0.5v to +4.0v maximum current into any pin ...........................................20ma operating temperature range .......................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -55c to +125c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ...................................... +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) tdfn junction-to-ambient thermal resistance ( ja ) .......... 60c/w junction-to-case thermal resistance ( jc ) ............... 11c/w absolute maximum ratings parameter symbol conditions min typ max units supply voltage v cc 2.97 3.3 3.63 v supply current i cc (note 3) 750 a sleep mode (slpz pin low), v cc = 3.63v 0.5 2.0 sha-256 engine computation current i csha refer to the full data sheet. ma computation time t csha ms eeprom programming current i prog (notes 4, 5) 2 ma programming time for 32-bit segment t prog refer to the full data sheet. ms write/erase cycling endurance n cy t a = +85c (notes 6, 7) 1000 data retention t dr t a = +85c (notes 8, 9, 10) 10 years slpz pin low level input voltage v il -0.5 0.3 x v cc v high level input voltage v ih 0.7 x v cc v cc + 0.5v v input leakage current i i pin at 3.63v 0.1 a wakeup time from sleep mode t swup (note 11) 250 s i 2 c scl and sda pins (note 12) low level input voltage v il -0.5 0.3 x v cc v high level input voltage v ih 0.7 x v cc v cc(max) + 0.5v v abridged data sheet downloaded from: http:///
ds28c22 deepcover secure memory with i 2 c sha-256 and 3kb user eeprom www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) (t a = -40c to +85c, unless otherwise noted.) (note 2) note 2: limits are 100% production tested at t a = +25c and t a = +85c. limits over the operating temperature range and rel - evant supply voltage range are guaranteed by design and characterization. note 3: operating current continuously reading the memory/mac read/write register at 400khz. note 4: guaranteed by design and/or characterization only. not production tested. note 5: refer to the full data sheet. note 6: write-cycle endurance is tested in compliance with jesd47g. note 7: not 100% production tested; guaranteed by reliability monitor sampling. note 8: data retention is tested in compliance with jesd47g. note 9: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. note 10: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated tem - peratures is not recommended. note 11: i 2 c communication should not take place for the max t oscwup or t swup time following a power-on reset or a wake-up from sleep mode. parameter symbol conditions min typ max units hysteresis of schmitt trigger inputs v hys (note 4) 0.05 x v cc v low level output voltage at 3ma sink current v ol 0.4 v output fall time from v ih(min) to v il(max) with bus capacitance from 10pf to 400pf t of (note 4) 60 300 ns pulse width of spikes suppressed by the input filter t sp (note 4) 50 ns input current with input voltage between 0.1v cc(max) and 0.9v cc(max) i i (notes 4, 13) -10 +10 a input capacitance c i (note 4) 10 pf scl clock frequency f scl 0 400 khz hold time (repeated) start condition, after this period, first clock pulse generated t hd:sta (note 4) 0.6 s low period of the scl clock t low (note 4) 1.3 s high period of the scl clock t high (note 4) 0.6 s setup time for repeated start condition t su:sta (note 4) 0.6 s data hold time t hd:dat (notes 4, 14, 15) 0.9 s data setup time t su:dat (notes 4, 16) 250 ns setup time for stop condition t su:sto (note 4) 0.6 s bus free time between stop and start condition t buf (note 4) 1.3 s capacitive load for each bus line c b (notes 4, 17) 400 pf oscillator warm-up time t oscwup (note 11) 250 s abridged data sheet downloaded from: http:///
ds28c22 deepcover secure memory with i 2 c sha-256 and 3kb user eeprom www.maximintegrated.com maxim integrated 4 note 12: all i 2 c timing values are referred to v ih(min) and v il(max) levels. note 13: i/o pins of the ds28c22 do not obstruct the sda and scl lines if v cc is switched off. note 14: the ds28c22 provides a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 15: the maximum t hd : dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the setup time before it releases the clock. (i 2 c-bus specification rev. 03, 19 june 2007) note 16: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda li ne tr max + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this setup time. (i 2 c-bus specification rev. 03, 19 june 2007) note 17: c b = total capacitance of one bus line in pf. the maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application. (i 2 c-bus specification rev. 03, 19 june 2007) electrical characteristics (continued) (t a = -40c to +85c, unless otherwise noted.) (note 2) pin coniguration pin description pin name function 1 scl i 2 c serial clock input. must be connected to v cc through a pullup resistor. 2 sda i 2 c serial data input/output. must be connected to v cc through a pullup resistor. 3 slpz active-low control input to activate the low-power sleep mode, and to issue a device reset. 4, 5, 7 n.c. no connection 6 v cc power-supply input 8 gnd ground reference ep exposed pad. solder evenly to the boards ground plane for proper operation. refer to application note 3273: exposed pads: a brief introduction for additional information. 1 + 3 4 8 6 5 gnd v cc n.c. ds28c22 2 7 n.c. scl slpz ep n.c. sda tdfn top view 1 + 3 4 8 6 5 28c22 ymrrf 2 7 ep top marking abridged data sheet downloaded from: http:///
ds28c22 deepcover secure memory with i 2 c sha-256 and 3kb user eeprom www.maximintegrated.com maxim integrated 36 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. note to readers: this document is an abridged version of the full data sheet. additional device information is available only in the full version of the data sheet. to request the full data sheet, go to www.maximintegrated.com/ds28c22 and click on request full data sheet . part temp range pin-package ds28c22q+t -40c to +85c 8 tdfn-ep * (2.5k pcs) package type package code outline no. land pattern no. 8 tdfn-ep t823+1 21-0174 90-0091 abridged data sheet downloaded from: http:///
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